The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that does not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted to be prior art against the present disclosure.
A counter is a logic circuit that is configured to output binary bits representing an incrementing integer at an edge of a clock signal. The counter usually includes one or more latch registers, e.g., D-latches, which are controlled by one or more clock signals. When all the D-latches in the counter are controlled by the same external clock signal, the counter is known as a synchronous counter. When only the first D-latch is controlled by an external clock, and all subsequent D-latches are controlled by the output of the preceding D-latch, the counter is known as an asynchronous counter. The asynchronous counter is also called a ripple counter because of the way the clock pulse “ripples” through the D-latches.
A multi-bit asynchronous counter is commonly used in integrated circuits to reduce power consumption relative to synchronous counters. As different latches in the asynchronous counter are not synchronized, gate propagation delays among the different latches in the circuit may limit the maximum input signal frequency and lead to counting errors when the counter output is sampled by another asynchronous clock.